OEES 235 Digital II

E235 11-29-11

ELT 235 Digital II
Bruce McDowell
e-mail address and phone
Fall 2011

Announcements

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Homework, Lab Work, & Class Exercises
H = homework, L = lab, CE = class exercise

Type	Assignment No.	Short Assignment Name	Date Assigned	Date Due	Points	Description
CE	KH18-28	Waveforms	8-18	8-25	15	Draw waveforms for the circuit of GH27-13 (AND, OR, D-FF). Handout
L	GH27-13	Lever schematic	8-18	8-25	20	Use the ispLever schematic editor to draw a circuit with an AND gate, OR gate, and a D flip-flop. Directions.
L	GI5-10	Lever simulation	8-18	8-25	20	Simulate the circuit from GH27-13. Directions.
L	KI15-35	Octave and Tone	9-15	9-27	20	Right-click here to get Web page. Also, get handout pages. Right-click here to download the test vector.
L	KI22-39	Serial to tone generator	9-27	10-4	15	Get handout sheets Right-click here to download the test vector file.
L	KI27-36	Octave select and 4 tones	9-27	10-6	25	Get handout sheets Right-click here to download the test vector file.
L	KJ04-33	Note-period memory	10-4	10-11	12	Get handout sheet Right-click here to download the schematic file Make your own test vector file
L	KJ06-35	Noise filter	10-6	10-13	10	Right click these files and download them: One-shot schematic One-shot symbol Noise-filter schematic Noise-filter test vector
L	KJ06-36	Noise filter 2	10-11	10-18	15	Web page
L	KJ18-34	AND-OR using Xilinx ISE	10-18	10-25	15	Web page
L	KJ18-36	OR-AND using Xilinx ISE	10-18	10-25	20	Create a new Xilinx project named KJ18-36 Put a copy of the main VHDL file and the test-bench file from KJ18-34 into the KJ18-36 folder. Rename the files kj18_36_or_and.vhd and kj18_36_or_and_tb.vhd, respectively. Modify both files to create a circuit with two 2-input OR gates feeding into a 2-input AND gate. Simulate the circuit.
L	KJ18-35	Counter	10-20	10-27	5	Get into the Xilinx Project Navigator. Click file, close project. Then, create a new Xilinx project named KJ18-35 Right-click to download these two files, and save them in the KJ18-35 folder: kj18_35_counter.vhd kj18_35_counter_tb.vhd Add these two source files to the project. Run the simulation.
L	KJ25-31	AND-OR Using Components	10-25	11-1	25	Get a handout sheet for the project. Download these files: kj25-31-AND-OR-using-components.vhd kj25-31-individual-gates.vhd kj25-31-individual-gates-2.vhd kj25-31-AND-OR-using-components_tb.vhd
L	KJ27-32	Edge detectors	10-27		15	Create a new project named kj27-32-edge-detectors Download these files into the project folder kj20_33_d_ff.vhd kj27-30-2-bit-dff-shift-register.vhd kj27-32-edge-detectors.vhd kj27-33-2and1.vhd kj27-32-edge-detectors-tb.vhd kj25-31-and-gate.vhd Create a third output called NO_CHANGE that will go high whenever there is not a rising or falling edge.
L	KK01-30	Edge detectors, behavioral	11-1	11-8	25	kk01_30_edge_detectors_behavioral.vhd kk01_30_edge_detectors_behavioral_tb.vhd
L	KK03_30	Windshield wiper	11-3	11-10	25	kk03_30a_windshield_wiper1_LAB.vhd kk03_30_windshield_wiper_tb.vhd kk03_30b_windshield_wiper2_LAB.vhd
L	KK08_30A	Wiper single cycle, second method	11-8		10	kk08_30_wiper_single_cycle_SECOND_METHOD.vhd kk08_30_wiper_single_cycle_tb.vhd
L	KK09_30	Shift register, behavioral	11-10	11-17	10	kk09_30_shift_reg2.vhd kk09_30_shift_reg2_tb.vhd
L	KK11-38	Shift and latch	11-15	11-29	30	Web page
L		Getting a Web Pack license	11-15		7
CE		Practice quiz	11-15		10
L	KK27_39	Counter and LEDs	11-29		10	Download: kk27_39_counter_and_LEDS_top.vhd kj18_35_counter.vhd kk27_39_counter_and_LEDS.ucf

Reference

Lever Macro Library Reference Manual OEES235 Custom Lever Macros
Hexadecimal Numbers

VHDL for FPGA Design (Wikibook)

Lever Macro Library Reference Manual	OEES235 Custom Lever Macros	Hexadecimal Numbers
VHDL for FPGA Design (Wikibook)