library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--Declaration of the module's inputs and outputs
entity and_or is port 
(
A: 	in 	std_logic;
B: 	in 	std_logic;
C: 	in 	std_logic;
D: 	in 	std_logic;
Y:  	out 	std_logic
); 
end and_or;

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--Defining the module's behavior
Architecture behavioral of and_or is 
	begin
		process (A, B, C, D) begin
	Y <= (A AND B) OR (C AND D);
	end process; 
end behavioral;
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