-- VHDL Test Bench Created by ISE for module: and_or

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY and_or_tb IS
END and_or_tb;
 
ARCHITECTURE behavior OF and_or_tb IS 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT and_or
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
         D : IN  std_logic;
         Y : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '1';
   signal B : std_logic := '0';
   signal C : std_logic := '0';
   signal D : std_logic := '0';

 	--Outputs
   signal Y : std_logic;
	signal ABCD: unsigned(3 downto 0) := (others => '0');

BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: and_or PORT MAP (
          A => A,
          B => B,
          C => C,
          D => D,
          Y => Y
        );
abcd_in : process
	begin
		A <= ABCD(0);
		B <= ABCD(1);
		C <= ABCD(2);
		D <= ABCD(3);
		ABCD <= ABCD + 1;
		wait for 10 ns;

	end process;
 
END;