-- VHDL Test Bench Created by ISE for module: and_or

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY counter_tb IS
END counter_tb;
 
ARCHITECTURE behavior OF counter_tb IS 
    -- Component Declaration for the Unit Under Test (UUT)
	 
	COMPONENT counter
		PORT(
			clr : in STD_LOGIC;
			clk : in STD_LOGIC;
			q : out STD_LOGIC_VECTOR(7 downto 0)
			);
	END COMPONENT;
  
	signal clr: std_logic := '1';
	signal clk: std_logic;
	signal q: std_logic_VECTOR(7 downto 0);


	BEGIN
	 
		-- Instantiate the Unit Under Test (UUT)
		uut: counter PORT MAP (
				clr => clr,
				clk => clk,
				q   => q
				);
		process
			begin
				wait for 10 ns;
				if (clr = '1') then
					clr <= '0';
				end if;	
				--clr <= '0'; 
				wait for 10 ns;
				clk <= '1'; wait for 10 ns;
				clk <= '0'; wait for 10 ns;
		end process;
	 
	END;