library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------
--Declaration of the module's inputs and outputs
entity and_or is 
	port 
	(
	A: 	in 	std_logic;
	B: 	in 	std_logic;
	C: 	in 	std_logic;
	D: 	in 	std_logic;
	Y:  	out 	std_logic
	); 
end and_or;

-------------------------------------------------------------------
--Defining the module's behavior
Architecture behavioral of and_or is 
	component and_gate is
		port
			(
			IN1 : in std_logic;
			IN2 :  in std_logic;
			OUTPUT : out std_logic
			);
	end component and_gate;
	
	component or_gate is
		port
			(
			IN1 : in std_logic;
			IN2 :  in std_logic;
			OUTPUT : out std_logic
			);
	end component or_gate;
	
	signal OUT1 : std_logic;
	signal OUT2 : std_logic;
	
	begin
	G1: and_gate port map (IN1 => A, IN2 => B, OUTPUT => OUT1);
	G2: and_gate port map (IN1 => C, IN2 => D, OUTPUT => OUT2);
	G3: or_gate port map (IN1 => OUT1, IN2 => OUT2, OUTPUT => Y);

end behavioral;
------------------------------------------------------------------