library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity d_ff is
   port
   (
      	CLK : in std_logic;
      	D : in std_logic;
			CLR : in std_logic;
			Q : out std_logic
   );
end entity d_ff;
 
architecture Behavioral of d_ff is
begin
   process (CLK) is
   begin
		if (CLR = '1') then
				Q <= '0';
		end if;
		
      if rising_edge(CLK) then  
			if (CLR ='1') then   
				Q <= '0';
			else				
				Q <= D;
			end if;
		end if;
	end process;
		
end architecture Behavioral;