library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity and_gate is 
	port 
	(
	IN1: 	in 	std_logic;
	IN2: 	in 	std_logic;
	OUTPUT:  	out 	std_logic
	); 
end and_gate;


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Architecture behavioral of and_gate is 
begin
		OUTPUT <= IN1 AND IN2;
end Architecture behavioral;
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