-- Test Bench for kj27-32 Edge Detectors   E235  11 1027
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY EDGE_DETECTORS_TB IS
END EDGE_DETECTORS_TB;
--========================================= 
ARCHITECTURE behavior OF EDGE_DETECTORS_TB IS  
	COMPONENT EDGE_DETECTORS
		PORT(
			CLK: 	in 	std_logic;
			INPUT: in 	std_logic;
			CLR: 	in 	std_logic;
			
			RISING: 	 out 	std_logic;
			FALLING:  out 	std_logic
			);
	END COMPONENT;
 --========================================
 	signal CLOCK : std_logic;
	signal DIN : std_logic;
	signal CLEAR : std_logic := '1';
	signal R_EDGE : STD_LOGIC;
	signal F_EDGE : STD_LOGIC;
	
	BEGIN
	 
		uut: EDGE_DETECTORS PORT MAP (
				CLK => CLOCK,
				INPUT => DIN,
				CLR => CLEAR,
				RISING => R_EDGE,
				FALLING => F_EDGE
				);
		process
			begin
				wait for 10 ns;
				if (CLEAR = '1') then
					CLEAR <= '0';
				end if;	
				wait for 10 ns;
				CLOCK <= '1'; wait for 10 ns;
				CLOCK <= '0'; wait for 10 ns;
		end process;
	 
	 	process
			begin
				DIN <= '0'; wait for 33 ns;
				DIN <= '1'; wait for 33 ns;			
		end process;

	END;