-- KJ27-32 Edge Detectors   E235   11 1017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity EDGE_DETECTORS is 
	port 
	(
	CLK: 	 in 	std_logic;
	INPUT: in 	std_logic;
	CLR: 	 in 	std_logic;
	
	RISING: 	 out 	std_logic;
	FALLING:  out 	std_logic
	); 
end EDGE_DETECTORS;
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Architecture behavioral of EDGE_DETECTORS is 
component two_bit_sr is
   port
   (
	CLK: 	in 	std_logic;
	INPUT: in 	std_logic;
	CLR: 	in 	std_logic;
	
	Q0OUT: 	out 	std_logic;
	Q1OUT:  	out 	std_logic
	);
end component two_bit_sr;
---------------
component TWO_AND_ONE is 
	port 
	(
	NONINVR: 	in 	std_logic;
	INVR: 	in 	std_logic;
	OUTPUT:  	out 	std_logic
	); 
end component TWO_AND_ONE;
--===========================================================
signal Q0_OUT : std_logic;
signal Q1_OUT : std_logic; 
signal R : std_logic;
signal F : std_logic;
--===========================================================
begin
SR: two_bit_sr port map 
	(CLK => CLK, INPUT => INPUT, CLR => CLR, Q0OUT => Q0_OUT, Q1OUT => Q1_OUT);
RE: TWO_AND_ONE port map 
	(NONINVR => Q0_OUT, INVR => Q1_OUT, OUTPUT => R);
FE: TWO_AND_ONE port map 
	(NONINVR => Q1_OUT, INVR => Q0_OUT, OUTPUT => F);
	
RISING <= R;
FALLING <= F;
end behavioral;