library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity TWO_AND_ONE is 
	port 
	(
	NONINVR: 	in 	std_logic;
	INVR: 	in 	std_logic;
	OUTPUT:  	out 	std_logic
	); 
end TWO_AND_ONE;


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Architecture behavioral of TWO_AND_ONE is 
begin
		OUTPUT <= NONINVR AND NOT INVR;
end Architecture behavioral;
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