--									E235  11 1101
-- Test Bench for kk01-30 Edge Detectors 
-- Using Data Flow   
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
entity Edge_detectors_tb is
end Edge_detectors_tb;
--========================================= 
architecture behavioral of Edge_detectors_tb is  
	component Edge_detectors
		port(
			clk: 		in 	std_logic;
			input: 	in 	std_logic;
		
			rising: 	out 	std_logic;
			falling:	out	std_logic
			);
	end component;
 --========================================
 	signal clock : 	std_logic := '0';
	signal din : 		std_logic := '0';
	signal r_edge : 	std_logic := '0';
	signal f_edge :	std_logic := '0';
	
	begin
	 
		uut: Edge_detectors port map (
				clk => clock,
				input => din,
				rising => r_edge,
				falling => f_edge
				);
		process
			begin
				clock <= '0'; wait for 10 ns;
				clock <= '1'; wait for 10 ns;
		end process;
	 
	 	process
			begin
				din <= '0'; wait for 73 ns;
				din <= '1'; wait for 73 ns;			
		end process;

end architecture behavioral;