-- KK09-30 Shift Register 2							E235   11 1109
--Behavioral instead of structural	

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity shift_reg2 is 
	port 
	(
		clk		:	in		std_logic;
		clr		:	in		std_logic;
		data_in	:	in		std_logic;
		q			:	out	std_logic_vector(3 downto 0)
	); 
end shift_reg2;

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architecture behavioral of shift_reg2 is 

signal qs	:	std_logic_vector(3 downto 0);
signal i		:  integer;

--=========================================
begin
	process (clk, clr) is
	begin
		if clr = '1' then
			for i in 0 to 3 loop
				qs(i) <= '0';
			end loop;		
		elsif clk'event and clk = '1' then
			qs(3) <= data_in;
			qs(2 downto 0) <= qs(3 downto 1);
		end if;		
	end process;
	q <= qs;
end behavioral;