-- Test Bench for KK09-30 Shift Register 2				E235   11 1109		

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY shift_reg2_tb IS
END shift_reg2_tb;
 
ARCHITECTURE behavioral OF shift_reg2_tb IS 
 	COMPONENT shift_reg2 is 
		port 
		(
			clk		:	in		std_logic;
			clr		:	in		std_logic;
			data_in	:	in		std_logic;
			q			:	out	std_logic_vector(3 downto 0)
		); 
	END COMPONENT;
  
	signal clksg		:	std_logic := '0';
	signal clrsg		:	std_logic := '1';
	signal data_insg	:	std_logic := '0';
   signal qsg			:	std_logic_vector(3 downto 0);
	
	BEGIN
		uut: shift_reg2	--Unit under test
		PORT MAP (
			clk		=> clksg,
			clr		=> clrsg,
			data_in	=> data_insg,
			q			=> qsg
		);
		
		process
		begin
			wait for 30 ns;
			clrsg <= '0';
		end process;
		
		process
		begin
			data_insg <= '0';
			wait for 30 ns;
			data_insg <= '1';
			wait for 30 ns;
			data_insg <= '0';
			wait for 30 ns;
			data_insg <= '1';
			wait for 60 ns;
		end process;
		
		process
		begin
			clksg <= '0';
			wait for 10 ns;
			clksg <= '1';
			wait for 10 ns;
			clksg <= '0';
			wait for 10 ns;
		end process;
END ARCHITECTURE;