-- KK11-37 N-Bit Register			E235   11 1111

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity reg is 
	generic (N: integer := 4);
	port 
	(
		load		:	in		std_logic;
		clk		:	in		std_logic;
		clr		:	in		std_logic;
		d			:	in		std_logic_vector(N-1 downto 0);
		q			:	out	std_logic_vector(N-1 downto 0)
	); 
end reg;

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architecture behavioral of reg is 
begin
	process (clk, clr) is
	begin
		if clr = '1' then
			q <= (others => '0');
		elsif rising_edge(clk) then
			if load = '1' then
				q <= d;
			end if;
		end if;		
	end process;
end behavioral;