-- KK11-38 Shift and Latch 			E235   11 1111

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity shift_latch is 
	generic (N: integer := 4);
	port 
	(
		--Latch the shift-register outputs into the register:
			latchit : in	std_logic; 
		--Clock:
			clk	:	in		std_logic;
		--Clear:
			clr	:	in		std_logic;
		--Serial data in:
			din	:	in		std_logic; -- Serial data

		--Shift register outputs:
			srq	:	out	std_logic_vector(N-1 downto 0)	
		--Register outputs:
			rq		:	out	std_logic_vector(N-1 downto 0);
	); 
end shift_latch;

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architecture behavioral of shift_latch is 
component shift_reg is 
	port 
	(
		. . .
	); 
end component;

component reg is 
	port 
	(
		. . .
	); 
end component;
	
signal clk_s, clr_s, data_in_s, latchit_s : std_logic;
signal srq_s, d_s, rq_s	: std_logic_vector(N-1 downto 0);

begin
	latchit_s 	<= latchit;		
	clk_s			<= clk;			
	clr_s 		<= clr;			
	data_in_s 	<= din;			




	
	U1: shift_reg
		port map 
		(	--Inputs
			clk 		=> clk_s,
			clr 		=> clr_s,
			data_in 	=> data_in_s,
			--Outputs
			q 			=> . . .
		);
	U2: reg
		port map
		(	--Inputs
			load		=>	latchit_s,
			clk		=>	clk_s,
			clr	   =>	clr_s,
			d		   =>	. . . ,
			--Outputs
			q			=>	. . .
		);

	--Send out the shift_latch outputs:
	srq <= srq_s;	--Shift register outputs.
	rq <= rq_s;		--Register outputs.
end behavioral;