-- Test Bench for KK11-38 Shift and Latch 	 E235   11 1111
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY shift_latch_tb IS
	generic (N:integer := 4);
END shift_latch_tb;
 
ARCHITECTURE behavioral OF shift_latch_tb IS 
component shift_latch is 
	port 
	(
		. . .
	); 
end component;
  
signal latchit_s	:	std_logic := '0';
signal clk_s		:	std_logic := '0';
signal clr_s		:	std_logic := '1';
signal din_s		:	std_logic := '0';
signal rq_s			:	std_logic_vector(N-1 downto 0);
signal srq_s		:	std_logic_vector(N-1 downto 0);
signal to_send		:	std_logic_vector(7 downto 0) := "10110010";
signal i				:	integer;

BEGIN
	uut: shift_latch	--Unit under test
	PORT MAP (
		latchit	=> latchit_s,	
		clk		=> clk_s,		
		clr		=> clr_s,		
		din		=> din_s,			
		rq			=> rq_s,
		srq		=> srq_s
	);
	-- CREATE THE CLEAR PULSE --------------------
	process
	begin
		wait for 30 ns;
		clr_s <= '0';
	end process;
	
	-- SEND SERIAL DATA ---------------
	process
	begin
	 --First 4-bit number:
		for i in 0 to 3 loop
			din_s <= to_send(i);
			wait for 30 ns;
		end loop;	
		din_s <= '0';
	
	
	
	 --Latchit pulse:
		latchit_s <= '1';
		wait for 30 ns;
		latchit_s <= '0';
		
	 --Second 4-bit number:		
		for i in 4 to 7 loop
			din_s <= to_send(i);
			wait for 30 ns;
		end loop;	
		din_s <= '0';
		
	 --Latchit pulse:
		latchit_s <= '1';
		wait for 30 ns;
		latchit_s <= '0';	
	end process;
	
	-- CLOCK --
	process
	begin
		--Sequence:
		--	clk_s goes low for 10 ns.
		--	clk_s goes high for 10 ns.
		-- clk_s goes low for 10 ns.
			. . .
	end process;
END ARCHITECTURE;