library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_and_leds_top is	
	generic(N : integer := 23);
	port (
		btn	: in std_logic_vector(0 downto 0);
		clk	: in std_logic;
		Led	: out std_logic_vector(7 downto 0)	
	);
end counter_and_leds_top;

architecture a_counter_and_leds_top of counter_and_leds_top is

component counter is
	generic(N : integer := 23);
	port(
	clr : in STD_LOGIC;
	clk : in STD_LOGIC;
	q : out STD_LOGIC_VECTOR(N-1 downto 0)
	);
end component;

signal q_s		: STD_LOGIC_VECTOR(N-1 downto 0);
	
begin
	COUNTER1: counter
	port map (
		--Inputs:
		clr	=> btn(0),
		clk	=> clk,
		--Outputs:
		q		=> q_s
		); 	
	Led(7 downto 0)	<= q_s(N-1 downto N-8);
end a_counter_and_leds_top;