OEES235

For this project, you'll be designing a block that accepts a binary number and then outputs a clock signal whose frequency increases by one octave for each increment in the binary number. This clock signal will be used to run the square wave generator that creates the output of the tone translator, and it will provide any octave shifting needed.

Here's an example of what this project's circuit should do:

If a binary seven is inputted to the circuit on the OCQ lines, the TONECLK output signal should be the same frequency as the CLK signal inputted to the circuit.

In another project, the OCQ input lines on this project lines will be connected to the outputs from the Octave Counter block.

For binary six, TONECLK should be the half the frequency of CLK.
For binary five, TONECLK should be one fourth the frequency of CLK.
For binary four, TONECLK should be one eighth the frequency of CLK.
Etc.
For binary zero, TONECLK should be 1/128th the frequency of CLK.

All you'll need is a counter and a multiplexer. One of your jobs is to determine how many bits the counter and the multiplexer need to be. A piece of information you'll need is that we want to be able to produce the musical note C that is 16.35 Hz and all the note inbetween up to a C of 2093 Hz. If you divide 2093 by 16.35, you'll get 128. Thus, if you start with a clock (CLK) frequency of 2093 Hz and use a counter with the right number of bits, the highest order bit will provide a frequency of 2093 divided by 128, which gives you 16.35 Hz.

By the way, the Lowest C on a piano keyboard is 32.7 Hz and the highest C is 4186 Hz. We're going to go one octave below this lowest C, which is 16.35 Hz. We won't be able to reach the 4186 Hz C, but we will be able to reach the B just below it (3951 Hz). I'm guessing we'd rather be able to hit the notes below 32.7 Hz rather than the ones 4186 Hz and above. If it turns out that my guess is wrong, we could either expand the octave range later, or switch the range to 32.7 Hz - 4186 Hz. After all, changes are easy to make on a PLD (programmable logic device).

Remember that for a binary counter, the low-order bit gives you a frequency half that of the clock. The next highest-order bit gives you a frequency one fourth that of the clock. And, the next one gives you one eighth the clock frequency, etc. Thus, as you go to higher- and higher-order bits, the octave goes down one step each time.

In order to determine how many bits you'll need, write down the binary weights until you get to 128. In other words, write down 1, 2, 4, 8, etc., multiplying by two each time until you reach 128. The number of weights you write down is the number of bits you'll need.

The binary number coming into this project's circuit on the OCQ lines will go to the select lines of the multiplexer, and the multiplexer's inputs will be connected to the counter's outputs. Thus, for each binary value put on the the multiplexer's select lines, the multiplexer will select a certain output line of the counter and then send it out on the multiplexer's single output line.

The OCQ bus shown in the waveforms above is composed of OCQ0, OCQ1, OCQ2, etc.

Right-click here to get the test vectors.

The test vector file contains a large number of clock pulses, as you can see from the solid line shown in the waveforms at the top of this page. (The line is solid because the clock pulses are too close together at this magnification.)

In the test vector file, the OCQ values start at 7 and then go 6, 5, 4, 3, 2, 1, 0. As the OCQ values decrease each time by one, you should see the period of TONECLK double. (In other words, the frequency will be halved each time.) You'll need to use the magnifier tool to see the waveforms at the beginning, and then you'll need to zoom out to see the ones at the end. There's no need to actually count the number of clock pulses. As long as your waveforms look like the ones shown at the top of the page, you're done.